The present invention relates generally to non-volatile memory devices and in particular the present invention relates to synchronous non-volatile flash memory with virtual segment architecture.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
Both RAM and ROM random access memory devices have memory cells that are typically arranged in an array of rows and columns. During operation, a row (page) is accessed and then memory cells can be randomly accessed on the page by providing column addresses. This access mode is referred to as page mode access. To read or write to multiple column locations on a page requires the external application of multiple column addresses. To increase access time, a burst mode access has been implemented. The burst mode uses an internal column address counter circuit to generate additional column addresses. The address counter begins at an externally provided address and advances in response to an external clock signal or a column address strobe signal.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ or 133 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. An extended form of SDRAM that can transfer a data value on the rising and falling edge of the clock signal is called double data rate SDRAM (DDR SDRAM, or simply, DDR). SDRAM""s can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory. A synchronous Flash memory has been designed that allows for a non-volatile memory device with an SDRAM interface. Although knowledge of the function and internal structure of a synchronous Flash memory is not essential to understanding the present invention, a detailed discussion is included in U.S. patent application Ser. No. 09/627,682 filed Jul. 28, 2000 and titled, xe2x80x9cSynchronous Flash Memory,xe2x80x9d which is commonly assigned and incorporated by reference.
In general, the goal of synchronous Flash is to mimic the architecture of SDRAM. It has an SDRAM interface which is compatible to SDRAM for read operation to the synchronous Flash memory. Programming, erasing, block protection and other flash specific function differ from SDRAM and are performed with a three cycle SDRAM command sequence. Unfortunately, the general internal architecture of conventional SDRAM memory is not the most efficient architecture for non-volatile memories and for Flash memory specifically.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation and maintain an internal architecture that is more applicable to non-volatile memory device access and power efficiencies.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a synchronous flash memory device comprises a first memory array with a first memory array dimensionality, a control circuit, and a synchronous memory interface, wherein the control circuit logically adapts the first memory array dimensionality to a second memory array dimensionality.
In another embodiment, a synchronous non-volatile memory device comprises a memory array with a plurality of array banks, each array bank having a first number of rows and a first number of columns, a control circuit, and a synchronous memory interface, wherein, for each array bank of the plurality of array banks, the control circuit logically adapts the first number of rows and the first number of columns to a second number of rows and a second number of columns.
In a further embodiment, a synchronous flash memory device comprises a first memory array with a first memory array dimensionality, a control circuit, wherein the control circuit logically adapts the first memory array dimensionality to a second memory array dimensionality, and a synchronous memory interface. Wherein the synchronous memory interface comprises, an address interface, a data interface, and a control interface.
In yet another embodiment, a synchronous flash memory device comprises a first memory array with a plurality of array banks, each having a first row dimension and a first column dimension, a control circuit, wherein the control circuit logically adapts the first row dimension and the first column dimension of each of the plurality of banks to a second row dimension and a second column dimension, and a synchronous memory interface. Wherein the synchronous memory interface comprises, an address interface, an extended address interface, a data interface, and a control interface.
A method of operating a synchronous flash memory device comprises dividing a memory array with a first memory array dimensionality into a plurality of sections, and logically adapting the plurality of sections of the memory array to form an emulated virtual second memory array dimensionality.
Another method of operating a synchronous flash memory device comprises dividing a memory array with a first memory array dimensionality into a plurality of array banks, dividing each array bank of the plurality of array banks into a plurality of segments, logically adapting the plurality of array banks and plurality of segments of the first memory array dimensionality of the memory array to form an emulated virtual second memory array dimensionality, wherein accessing the emulated virtual second memory array dimensionality occurs through a synchronous memory interface, and allowing access to the first memory array dimensionality of the memory array through the synchronous memory interface and an extended interface.
In yet another method of logically mapping a synchronous non-volatile memory device comprises forming a first memory array with a first plurality of banks, dividing each bank of the first plurality of banks into a plurality of segments, and logically mapping the plurality of segments to appear as a second memory array with a second plurality of segments.
In a further embodiment, a synchronous flash memory device comprises a memory array with a first set of four array banks, such that each array bank has a first number of rows and a first number of columns and each array bank is divided into four segments by row range, a latch circuit, a control circuit, and an SDRAM compatible synchronous memory interface. Wherein the control circuit logically maps the latch circuit and the four segments in each of the four array banks to appear as an emulated virtual SDRAM memory device of an equal memory size with a second virtual set of four array banks, such that the first number of rows and the first number of columns of each array bank of the memory array map to a second number of rows, that is one fourth the first number of rows, and a second number of columns, that is four times the first number of columns, of the second virtual set of four array banks of the emulated virtual SDRAM memory device.
In another method of making a synchronous flash memory device comprises forming a non-volatile memory array with a plurality of array banks, each array bank having a first number of rows and a first number of columns, forming a control circuit, and forming a synchronous interface, wherein the control circuit logically adapts the first number of rows and the first number of columns of each array bank of the plurality of array banks to a second number of rows and a second number of columns.
In another embodiment, a system comprises a synchronous memory controller, and a synchronous flash memory device. Wherein the synchronous flash memory device comprises, a memory array with a first memory array dimensionality, a control circuit, and a synchronous memory interface, wherein the control circuit logically adapts the first memory array dimensionality to a second memory array dimensionality.